Start-up automatic frequency control (AFC) method and apparatus

ABSTRACT

Method and apparatus for adjusting the frequency of a VCO at a receiver to synchronize the receiver with the transmitter by correlating a synchronization code channel with training sequences to estimate positive and negative offsets which are employed to estimate an error, which is then filtered. The filter output provides voltage controlling the VCO. The same technique may be employed to control a numeric controlled oscillator (NCO).

CROSS REFERENCE TO RELATED APPLICATION(S)

[0001] This application claims priority from U.S. provisionalapplication No. 60/399,818 filed on Jul. 31, 2002, which is incorporatedby reference as if fully set forth.

FIELD OF THE INVENTION

[0002] The invention relates to a wireless communication system. Moreparticularly, the invention relates to initialization of a communicationlink between a base station (BS) and a user equipment (UE).

BACKGROUND OF THE INVENTION

[0003] During an initial cell search (ICS) or power-up of a UE, atraining sequence of known symbols is used by the receiver to estimatethe transmitted signal. In a time division duplex (TDD) signal, forexample, the midamble of a TDD frame conventionally contains thetraining sequence of symbols. The conventional cell search processconsists of a Step 1 algorithm which processes a primary synchronizationcode (PSC) on the primary synchronization code channel (PSCH) forsynchronization channel (SCH) location determination. A Step 2 algorithmprocesses the secondary synchronization codes (SSC) for code groupdetermination and timeslot synchronization, and a Step 3 algorithmperforms midamble processing.

[0004] Variable control oscillators (VCOs) are commonly used at the endof an automatic frequency control (AFC) process to adjustably controlthe frequency of the receiver to achieve synchronization between atransmitter and a receiver. The input for the VCO is a control voltagesignal, which is typically generated by a control circuit that processesthe amplitude and phase of the received symbols. A common problem duringan AFC process is the initial fluctuations resulting from a potentiallysignificant frequency offset between the transmitter and the receiver.

SUMMARY

[0005] A method and apparatus for adjusting the frequency of a VCO at areceiver to synchronize the receiver with the transmitter by correlatinga synchronization code channel with training sequences to estimatepositive and negative offsets which are employed to estimate an error,which is then filtered. The filter output provides a voltage controllingthe VCO. The same technique may be employed to control a numericcontrolled oscillator (NCO).

BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The invention will be understood from the following descriptionand drawings in which like elements are designated by like numerals and,wherein:

[0007]FIG. 1 is a block diagram showing the phase rotation approach forstartup AFC.

[0008]FIGS. 2A and 2B, taken together, comprise a block diagram of theinteraction between start-up AFC and algorithm Steps 1, 2 and 3 of cellsearch.

[0009]FIG. 2 shows the manner in which FIGS. 2a and 2 b are arranged tocreate a complete block diagram.

[0010]FIG. 3 shows a process diagram for a PI filter.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT(S)

[0011]FIG. 1 is a block diagram of a start-up adaptive frequency control(AFC) 10 used to reduce the frequency offset between a base station (BS)and user equipment (UE) during initial cell search procedure. Start-upAFC uses a phase rotation approach, which is based on the correlationsof two sequences with the primary synchronization code (PSC). The storedPSC sequence 12 is rotated in opposing directions at 14, 14 a, 16, 16 ato respectively determine correlations with the received sequence 18 at20 and 22. The absolute values (a and b) are obtained at 24 and 26 andto obtain the value${\left( \frac{a - b}{a + b + c} \right)6\quad {kHz}},$

[0012] from circuit 27, where c is an arbitrary constant provided toprevent division by zero. The phase rotation at −3 kHz alternatively canbe replaced by a conjugate of a rotated PSC sequence at 3 kHz since thePSC sequence can only have values of (1+j) and (−1−j).

[0013] During start-up AFC process, it is assumed that the PSC locationprovided is correct. Once Step 1 completes generation of the firstoutputs, the start-up AFC starts running. The Step 1 process andstart-up AFC process run in parallel. Optimally, start-up AFC reducesthe frequency offset from 6 kHz to less than 2 kHz in the least numberof iterations. Table 1 shows a particular advantage of frequencycorrection which is an increase in allowable integrations. The number ofintegrations is limited, however, due to chip slip. The chip-slip upperbound is 0.5Tc since the maximum correlation is generated one samplelater for a method utilizing twice the chip rate sampling. Table 1summarizes the allowable number of integrations as frequency offset isreduced. Table 2 provides information on performance degradation for acoherent combining technique in the presence of carrier frequencyoffset. TABLE 1 Frequency Offset vs. Number of Integration AllowedFrequency Offset Slip per frame Number of integrations allowed ±6 kHz =±3 ppm 0.1152 Tc 4 ±4 kHz = ±2 ppm 0.0768 Tc 6 ±2 kHz = ±1 ppm 0.0384 Tc13 ±1 kHz = ±0.5 ppm 0.0192 Tc 26

[0014] TABLE 2 Frequency Offset vs. Code Length for Coherent CombiningLength of the code Carrier frequency Offset Loss in dB integratedcoherently Fc = 2 GHz 2.42 256   ±3 ppm 6 kHz 1.04 256   ±2 ppm 4 kHz0.26 256   ±1 ppm 2 kHz 0.06 256 ±0.5 ppm 1 kHz 12.62 512   ±3 ppm 6 kHz4.53 512   ±2 ppm 4 kHz 1.04 512   ±1 ppm 2 kHz 0.26 512 ±0.5 ppm 1 kHz

[0015] The start-up AFC procedure includes a mechanism to realign theprimary synchronization code (PSC) position that may shift duringcorrection. The Step 1 procedure can be run to eliminate the need forthe mechanism while the start-up AFC algorithm is running. The Step 1procedure updates the peak location every 4th frame.

[0016]FIG. 2 depicts the parallel processing relationship among start-upAFC and Steps 1, 2 and 3 of cell searching. Of particular concern is therelationship between Step 1 and start-up AFC. Since Step 1 works inparallel with the startup AFC, there is no need for a code trackercircuit to follow a given path. Each time Step 1 updates an output thatis based on the largest detected value, start-up AFC uses the new peaklocation to estimate the new frequency offset.

[0017] The frequency estimator block (FEB) 31 of the start-up AFCcomprises a Sequence Locator and Splitter 32, frequency estimators34-38, a proportional plus integral (PI) filter 42, and a voltagecontrolled oscillator (VCO) or numeric controlled oscillator (NCO) 46coupled to PI filter 42 through the sign flop 44. The input 32 a to theSequence Locator and Splitter 32 includes the PSC peak locationchip-offset provided by Step 1. Start up AGG 30 is an open loop gaincontrol block that steps through pre-defined gain levels in order to setproper input power level before digitizing the input. The main input toboth Step 1 and the Sequence Locator and Splitter 32 is sampled at twicethe chip rate with a length of 76,800 complex elements. Since thechip-offset points to the peak location, the beginning of the PSC is 511samples before the chip-offset. The outputs of the Sequence Locator andSplitter 32 are generated by the following general equation:

Output=input[i−511]i  Eq. (1)

[0018] Accordingly, the three particular outputs of the Sequence Locatorand Splitter 32 are represented by the following equations for early (32b), punctual (32 c) and late 32(d) estimates:

Early[i]=input[i−511]i=offset−1, offset, offset+1, . . . ,offset+510  Eq. (2)

Punctual[i]=input[i−511]i=offset, offset+1, offset+2, . . . ,offset+511  Eq. (3)

Late[i]=input[i−511]i=offset+1, offset+2, offset+3, . . . ,offset+512  Eq. (4)

[0019] Although the Locator and Splitter 32 in the example given in FIG.2, is a PSC locator, it should be understood the same approach can beused with any received sequences other than PSC.

[0020] The input samples to the Sequence Locator and Splitter are takenat twice the chip rate.

[0021] The frequency estimators 34, 36 and 38 each receive one of thethree inputs provided by Equations (2)-(4). The frequency estimatorsestimate a different frequency offset, summed at 40, for each inputsequence in accordance with FIG. 1. The frequency offset, summed at 40,is the summation of early, punctual and late estimates.

[0022] The sum of the estimates is passed through a proportional plusintegral (PI) filter 42 with coefficients alpha and beta, respectivelyas shown in detail in FIG. 3. The PI filter bandwidth has two settings.Initially, alpha and beta are preferably ½ and {fraction (1/256)},respectively as shown in detail in FIG. 3. The loop gain k is set at(k=−1.0). During steady state, alpha and beta are set to {fraction(1/16)} and {fraction (1/1024)}, respectively. FIG. 3 depicts such a PIfilter structure 42. The preferable settings for coefficients alpha andbeta are summarized in Table 3. However, other filters may besubstituted for the PS filter. TABLE 3 PI Filter Coefficients as aFunction of Operating Conditions. Condition alpha beta initial 1/2 1/256  steady state 1/16 1/1024

[0023] Steady state condition is established when:

[0024] the startup AFC completes at least ten (10) iterations;

[0025] while the last eight (8) outputs (inputs to VCO) are put into abuffer of length eight (8); the difference between the absolute value ofthe average of the first half and that of the second half is within ±1kHz; and

[0026] the current output to the VCO is within ±1 kHz of the absolutevalue of the average of the second half.

[0027] For digital applications, a numerically controlled oscillator(NCO) is used in place of the VCO.

[0028] The start-up AFC algorithm relies on PSC location update toestimate the carrier frequency offset. Step 1 runs during frequencycorrection to update the PSC location. As such, it is preferable thatstart-up AFC is begun immediately following a successful Step 1 process,with Step 1 running in parallel. Step 1 continues to provide updated PSClocations once every N1 frames as per the Step 1 algorithm, where N1 isthe maximum number of frames for averaging. Start-up AFC is run in thismanner for a duration of L frames, with L=24 as the preferred value. TheStep 1 FLAG 61 from controller 60 is set when a sequence is detected.The FEB 31 runs when the controller 60 provides an enable condition toFEB 31 at 62. Since the peak locations shift left or right in time, theStep 1 algorithm is run constantly. At the end of L frames, the startupAFC reduces the frequency offset to about 2 KHz in many cases, whichprovides considerable enhancement to the Step 2 performance. Theinclusion of L frames contributes to the overall cell search delaybudget and hence is chosen conservatively to be L=24.

[0029] PSC processing block 66 correlates against the primarysynchronization code in (synchronization channel) (SCH) over frames. TheSCH location is not known.

[0030] SSC extractor block 68 utilizes the SCH location and extractsonly the SCH portion, which is then passed to SSC processing block 70.

[0031] SSC processing block 70 correlates against the secondarysynchronization code in synchronization channel over SCH.

[0032] Midamble Extractor block 72 utilizes the SCH location and SSCprocessing results and extracts the midamble portion to pass to midambleprocessing block 74.

[0033] Midamble processing block 74 correlates against possiblemidambles given by SSC processing and picks the one with the highestenergy.

[0034] Periodic Cell Search block 76 performs a process which constantlysearches for the best base station for the given period.

[0035] Controller 60 coordinates among stages to synchronize to a basestation.

[0036] Layer 1 Controller 80 coordinates all layer 1 related hardwareand software in order to maintain proper operation in the receiver.

What is claimed is:
 1. A start-up automatic frequency control (AFC)method used during initial cell search (ICS) processing by a userequipment (UE) receiver, where the ICS comprises Step 1 processing of agiven sequence, the method comprising: a) receiving said sequence; b)rotating a phase of the sequence; c) correlating a primarysynchronization channel (PSCH) sequence with the rotated phase of thereceived sequence and an unrotated phase of the received sequence; andd) integrating the two correlations of step (c), whereby the AFCstart-up method is performed in parallel with the Step 1 sequenceprocessing.
 2. The method of claim 8 wherein the given sequence is aprimary synchronization code (PSC) sequence.
 3. The method of claim 1further comprising repeating steps (b) to (d) a given number of times.4. The method of claim 3 wherein steps (b) to (d) are preferablyrepeated twenty-four (24) times.
 5. A system for performing start-up AGCduring initial cell search (ICS) by a user equipment (LTE) receiver,where the ICS comprises Step 1 processing of a given sequence,comprising: a first correlator for receiving a first stored sequence ofthe primary synchronization channel; a second correlator for receiving asecond stored sequence of the primary synchronization channel; an errorestimator for determining the error associated with the outputs of thefirst and second correlators; a filter for selectively integrating theerror estimate responsive to an initial or steady state conditions ofthe cell search process; and one of a voltage controlled oscillator(VCO) and numeric controlled oscillator (NCO) for adjusting frequencyresponsive to the integrated error estimate.
 6. The system of claim 5wherein the given sequence is a primary synchronization code (PSC)sequence.
 7. The system of claim 5 wherein the filter is a PI filter. 8.The system of claim 5 wherein said filter is a digital filter having adelay element of 1/(1−z⁻¹).
 9. The method of claim 1 wherein: a receivedinput power level is adjusted prior to steps (a) to (d).
 10. The methodof claim 9 wherein the input is digitized after adjustment of the powerlevel.
 11. The method of claim 9 wherein the power level is setemploying open loop gain control.
 12. The method of claim 1 wherein thestep of ICS processing includes: obtaining the primary synchronizationcode (PSC).
 13. The method of claim 12 further comprising: employing thePSC to extract the secondary synchronization code (SSC) from thereceived input.
 14. The method of claim 13 wherein the received PSC andSSC are utilized to extract a midamble portion from the received input.15. The method of claim 14 wherein a midamble having a highest energy isselected from the extracted midamble portion.
 16. The method of claim 1wherein a periodic cell search is conducted to obtain a best basestation during a given period.
 17. The method of claim 1 wherein thefrequency adjustment is numerically controlled.
 18. The method of claim1 wherein the frequency adjustment is voltage controlled.
 19. The methodof claim 1 wherein the Step 1 processing is repeated every N1 frameswhere N is a real integer and N≧1.
 20. A method for adjusting frequencyduring an initial cell search in a wireless network, comprising: a)obtaining a synchronization code responsive to a received inputcontaining a sequence; b) rotating a phase of the sequence; c)correlating a primary synchronization channel (PSCH) sequence with therotated phase of the received sequence and an unrotated phase of thereceived sequence; and d) integrating the two correlations of step (c),whereby the AFC start-up method is performed in parallel with step (a).